Mrad test circuit, semiconductor memory device having the same and mrad test method

Abstract

A multi-row active disturb (MRAD) test circuit, a semiconductor memory device having the test circuit, and an MRAD test method are provided. The semiconductor memory device includes at least one memory array including a plurality of word lines sharing a bit line sense amplifier. Furthermore, in the semiconductor memory device, at least two word lines among the plurality of word lines, which have a bit line sense amplifier in common, are activated simultaneously in an MRAD test mode. The test circuit includes a control signal generating circuit and a row decoder. The control signal generating circuit is a circuit for generating a plurality of control signals and generates at least one activated control signal in an MRAD test mode. The row decoder activates at least two word lines by a control signal and a predetermined row address signal comprised of a plurality of bits. The test circuit and the test method provide a reduction in test time for a semiconductor memory device without increase in current consumption.