The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 09, 2001
Filed:
Jan. 19, 2001
Amrit P. Patel, Camarillo, CA (US);
Power-One, Inc., Camarillo, CA (US);
Abstract
A power converter has a self-driven synchronous rectification circuit that can operate efficiently with a non-optimal reset secondary voltage waveform that remains at a zero voltage level during a portion of the switching cycle. The power converter circuit includes a transformer having a primary winding and a secondary winding, in which primary winding is supplied with a non-optimal reset waveform that remains at a zero voltage level for a portion of a power cycle thereof. A first synchronous rectifier is connected in series with the first end of the secondary winding and is controlled by a voltage at the second end of the secondary winding. A second synchronous rectifier is connected in series with the second end of the secondary winding, and is further connected to an output terminal of the power converter circuit through a storage choke. A saturable reactor is connected in series between the first synchronous rectifier and the first end of the secondary winding. A switching device is connected to the first end of the secondary winding and is controlled by the voltage at the second end of the secondary winding. The switching device further controls the second synchronous rectifier. A capacitor is connected to the second synchronous rectifier, and is charged by operation of the switching device to maintain the second synchronous rectifier in a conductive state during the zero voltage level portion of the non-optimal reset waveform. Upon transition to a positive voltage level portion of the waveform following the zero voltage level portion, the capacitor discharges through the switching device. The saturable reactor precludes current from flowing through the first synchronous rectifier for a period of time sufficient to allow the capacitor to discharge.