The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 09, 2001

Filed:

Jun. 19, 2000
Applicant:
Inventor:

Douglas Scott Piasecki, Austin, TX (US);

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03M 1/00 ;
U.S. Cl.
CPC ...
H03M 1/00 ;
Abstract

A system on chip with ADC having serial test mode. An integrated circuit having a processing system with a system clock and a data conversion circuit is provided that is operable to convert data between the analog and the digital domain, the data converter utilizing the system clock during normal operation. A clock isolation circuit is provided for isolating the operation of the data converter from the system clock during a test mode. A serial clock is provided for generating a serial clock during the test mode independent of a system clock. Control circuitry is then operable for controlling the data converter during the test mode to convert data utilizing the serial clock at times not coinciding with the rising and falling edges of the system clock, such control circuit operating in response to receiving a test control signal.


Find Patent Forward Citations

Piasecki, Douglas. (2001). System on chip with adc having serial test mode (U.S. Patent No. 6300889). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6300889

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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