Method and apparatus for cascaded ground return amplifier

Abstract

A cascaded amplifier is integrated within an integrated circuit with a cascaded ground bus. The cascaded ground bus provides two ground points at opposite ends. Each amplifier ground of each amplifier stage couples to the ground wire there between. The cascaded ground bus substantially reduces the parasitic inductance in the emitter leg of each IC transistor within each amplifier. The lay out of the cascaded ground bus wire is tightly coupled to the lay out of the input wires so that their respective parasitic inductances are magnetically coupled together to form a mutual inductance. The mutual inductance effectively cancels the effect of the ground return inductance due to them being similar inductance values and having the same ground loop current flowing through them in opposite directions. The cascaded ground bus can be utilized in substantially all amplifier types including class A, B, C, D, BD, E, F, G, H, S and their variations and with substantially all transistor types used within amplifier stages including bipolar junction transistors, field effect transistors and their variants (i.e. PNP, NPN, MOSFET, NFET, PFET, JFET, MESFET, etc.). An IC cascaded amplifier with the cascaded ground bus can be utilized in a number of communication systems where amplification is needed including battery operated systems such as a transceiver of a portable cellular telephone.