Timing-control circuit device and clock distribution system

Abstract

A timing-control circuit device, which uses a synchronous mirror delay circuit, for keeping the synchronization between clock signals in phase even at a load change. A reference clock signal (clkin,) is entered to a timing-control circuit (SMDF,) and used to generate an internal clock (dclk,), then generates an external clock (clkout,) through a buffer (BUF,). The external clock signal is fed back to the timing-control circuit (SMDF,) and used to generate an internal clock signal so as to synchronize the external clock signal in phase with the reference clock signal. The timing-control circuit is provided with a circuit (FDA,, MCC,) for detecting a phase difference between the internal clock signal and the external clock signal, as well as a delay circuit (DCL,) for controlling a delay time, so that the delay circuit (DCL,) can change the delay time according to the detected phase difference.