Process for manufacturing semiconductor integrated memory devices with cells matrix having virtual ground

Abstract

A process for manufacturing electronic semiconductor integrated electronic memory devices having virtual ground and including at least a matrix of floating gate memory cells formed on a semiconductor substrate with a plurality of continuous bit lines extending across the substrate as discrete parallel strips begins with forming an oxide layer over the matrix region. Then, the semiconductor throughout is deposited with a stack structure which includes a first conductor layer, a first dielectric layer, and second conductor layer. Next, a second dielectric layer is formed. Floating gate regions are defined by photolithography using a mask of “POLY,along a first predetermined direction”, and associated etching, to define, in the stack structure, a plurality of parallel openings. These openings are implanted to confer a predetermined conductivity on the bit line regions. Next, the parallel openings are filled with a photo-sensitive material to protect the matrix bit lines.