Digital-to-analog converter with high-speed output

Abstract

A digital-to-analog converter (DAC) includes separate converter segments for converting the most significant bits (MSB's) and next-most-significant bits (NSB's) of a digital input word. The MSB's are converted in a thermometer-encoded capacitive DAC (CDAC), in which the MSB's are decoded and used to control the state of CDAC switches, which connect any of a plurality of CADC reference voltages, through respective unit capacitors, to the DAC output. The NSB's are converted in a preferably binary encoded resistive DAC (RDAC), in which two separate sets (“A” and “B”) of RDAC switches selectively connect a plurality of RDAC reference voltages to respective A and B RDAC output buses. Control circuitry is included to decode and apply the MSB's as state control signals to the CDAC switches on each clock cycle. The NSB's are also decoded and applied as control signals, but on alternate clock cycles, to the A and B RDAC switch sets. Bus selection circuitry is included to select which of the A or B RDAC output buses is connected to the system output, via an RDAC output capacitor. The RDAC output thus alternates between the A and B RDAC switch sets, thereby ensuring that each set of switches will have time to settle before it is allowed to influence the output. Least significant bits (LSB's) (selected as a lower significance portion of the NSB's) are preferably separately converted in an LSB RDAC that has the same structure, control circuitry, and alternating control pattern, as the NSB, but with a down-scaling output capacitor. The DAC according to the invention thereby provides a high conversion rate with very low glitch disturbances.