The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 02, 2001

Filed:

Nov. 23, 1999
Applicant:
Inventors:

Thomas A. Weingartner, Albuquerque, NM (US);

Paul J. Short, Albuquerque, NM (US);

Mark A. Espelien, Albuquerque, NM (US);

Jordon W. Woods, Albuquerque, NM (US);

Assignee:

InnoVasic, Inc., Albuquerque, NM (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/500 ;
U.S. Cl.
CPC ...
H01L 2/500 ;
Abstract

A method and apparatus for a fully programmable and configurable application specific integrated circuit (FPCA). Programmable I/O cells are programmed for selected electrical characteristics, including power and ground. The circuit contains a functional core for programming the circuit, programmable I/O leads to connect to the programmable I/O cells, and programming logic and control for programming the functional core and I/O cells. Certain leads double as programmable I/O leads and programming control leads, and are used to communicate with the programming logic and control and the I/O cells. A method of programming the FPCA comprises the steps of asserting the programming control signal; applying programming voltage and ground to a respective two designated I/O cells' leads; isolating a plurality of the I/O cells from the programming signal; and programming an FPGA array in addition to the isolated I/O cells of the circuit.


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