Real time interrupt handling for superscalar processors

Abstract

A CPU includes a real time interrupt (RTI) control unit configured to control real time interrupt capabilities of the CPU. Upon receipt of a real time interrupt signal via an RTI pin, the RTI control unit interrupts the currently executing instructions at an instruction boundary in order to execute the interrupt service routine. Instead of using the interrupt acknowledge cycles normally used to locate an interrupt vector, and then using the interrupt vector to locate an interrupt descriptor, the interrupt descriptor is stored in an RTI register coupled to the RTI control unit. In one embodiment, the CPU is configured not to save processor context upon initiation of a real time interrupt. Instead, as register resources are needed by the real time service routine, these resources are allocated. Registers allocated for real time use are indicated in the RTI register. In yet another embodiment, the CPU is configured with lockable cache lines in the instruction and data caches. An RTI bit is defined in the code and data segment descriptors for indicating whether or not the code/data within the segment is real time code/data (i.e. is used in an RTI service routine). The code/data within these segments is locked into the instruction and/or data cache. The cache replacement algorithm employed by the cache attempts to select a non-locked cache line for storing a cache line being transferred into the cache.