Point-to-point interrupt messaging within a multiprocessing computer system

Abstract

An interrupt messaging scheme to manage interrupts within a multiprocessing computer system without a dedicated interrupt bus. An interconnect structure using a plurality of high-speed dual-unidirectional links to interconnect processing nodes, I/O devices or I/O bridges in the multiprocessing system is implemented. Interrupt messages are transferred as discrete binary packets over point-to-point unidirectional links. A suitable routing algorithm may be employed to route various interrupt packets within the system. Simultaneous transmission of interrupt messages from two or more processing nodes and I/O bridges may be possible without any need for bus arbitration. Interrupt packets carry routing and destination information to identify source and destination processing nodes for interrupt delivery. A lowest priority interrupt packet from an I/O bridge is converted into a coherent form by the host processing node coupled to the I/O bridge. The host node then broadcasts the coherent interrupt packet to all other processing nodes in the system regardless of whether a processing node is identified as a target in the interrupt message packet from the I/O bridge. The host node also receives responses from recipient nodes and coordinates lowest priority arbitration. In case of a fixed, an ExtINT or a non-vectored interrupt message from the I/O bridge, the host node simply forwards the interrupt packets to all other nodes in the system without performing the conversion. Inter-processor interrupts may also be delivered in a similar manner. Interrupt response is decoupled from corresponding interrupt message and the interrupt messaging protocol may be implemented independently of the physical properties of a system bus carrying interrupt packets.