The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 25, 2001
Filed:
Sep. 28, 1998
Daniel M. Clementi, Doylestown, PA (US);
American Microsystems, Inc., Pocatello, ID (US);
Abstract
A spread-spectrum modulation method and circuit for a clock generator phase-locked loop (PLL). A dither signal is injected into a PLL in synchronization with and having the same period or fraction of the same period as the phase comparison performed within the PLL. Over such period, the phase error caused by the modulation will integrate to zero and hence avoid transmitting a disturbance to the loop. A particular embodiment utilizes an output of the reference divider and/or feedback divider within the PLL to generate the dither signal. Such a configuration avoids the need for additional hardware which otherwise would increase the chip area and/or cost of the device. The reference divider and/or feedback divider is made up preferably of a linear feedback shift register (LFSR). One or more stages of the LFSR provide an output which is used to generate the dither signal. In a preferred embodiment, the output from the LFSR exhibits a pseudo-random sequence.