Programmable logic device with highly routable interconnect

Abstract

A programmable logic device architecture with a highly routable programmable interconnect structure. The arrangement of the logic array blocks (LABs), programmable interconnect structure, and other logical elements forms a Clos network. After specific constraints have been met, the architecture is guaranteed to route. The architecture is provably routable when there is no fan-out in the middle stage. A LAB (A-,) comprises an input multiplexer region (A-,), logic elements (A-,), input-output pins (A-,), and output multiplexer region (A-,). Furthermore, a logic device and a method of operating a logic device. The device includes logic elements (B-,) that perform desired logic functions and routing functions. The logic elements (B-,) are arranged in larger logic blocks known as logic array blocks (B-,) that have local interconnection systems. The logic array blocks (B-,) are configured to provide global interconnections. The configuration provides a Clos network, whereby a signal may be routed from any input to any output without blocking.