The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 25, 2001

Filed:

Mar. 16, 2000
Applicant:
Inventors:

Dau-Tsuong Lu, Clifton Park, NY (US);

John T. Keating, Clifton Park, NY (US);

Assignee:

Performance Interconnect, Inc., Schenectady, NY (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H05K 9/00 ;
U.S. Cl.
CPC ...
H05K 9/00 ;
Abstract

The present invention comprises a high performance single chip or multi-chip package which combines a CTE controlled electronic substrate, a multi-layer interconnect, bare dice or packaged devices, a top layer encapsulant and an interposer to provide a compliant and de-mountable connection to a printed circuit board. The CTE controlled electronic substrate comprises a metal or composite shell around an encapsulated core holding vertical electrical conductors. The vertical connection comprises an array of stranded or braided electrical conductors which may be exposed on the top and or bottom of the electronic substrate to provide a de-mountable interface. An interconnect layer may be attached to the planar CTE controlled electronic substrate using an adhesive or polymer. Following the connection of the interconnect to the substrate, the bare dice and/or package may be attached to the interconnect.


Find Patent Forward Citations

Loading…