The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 25, 2001
Filed:
Dec. 10, 1999
Abu-Hena Mostafa Kamal, Sunnyvale, CA (US);
National Semiconductor Corporation, Santa Clara, CA (US);
Abstract
Process for the formation of a polysilicon layer with a controlled, small silicon grain size that includes first providing a semiconductor substrate (such as a silicon wafer), followed by the formation of a silicon dioxide layer (such as a gate silicon dioxide layer) on the semiconductor substrate. Next, an amorphous silicon layer is deposited on the silicon dioxide layer. The amorphous silicon layer can be deposited using LPCVD at a temperature in the range of 520° C. to 560° C. and a pressure in the range of 150 mTorr to 250 mTorr. Next, a plurality of silicon crystallites are formed in the amorphous silicon layer by subjecting it to a first RTA cycle at a temperature in the range of 750° C. to 850° C. for a time period of 30 seconds to 90 seconds and a temperature ramp rate of at least 50° C. per second. Finally, the amorphous silicon layer with silicon crystallites is subjected to at least one additional thermal cycle, thereby growing the silicon crystallites into small silicon grains and forming a polysilicon layer with controlled, small silicon grain size.