The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 18, 2001
Filed:
Feb. 20, 1998
Applicant:
Inventor:
Guy Dupenloup, Marly-le-Roi, FR;
Assignee:
LSI Logic Corporation, Milpitas, CA (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/750 ;
U.S. Cl.
CPC ...
G06F 1/750 ;
Abstract
A method of determining circuit characteristics of an integrated circuit design defined by RTL code, said method comprising the steps of identifying hardware elements in the RTL code, determining key pins for said identified hardware elements, and extracting critical design structure from the RTL code. The hardware elements identified include flipflops, latches, tristate buffers, bidirectional buffers and memories. The critical design structures include design hierarchy and nets, including clock nets, multiply-driven nets, reset nets, and RAM write enable nets.