Method of design for testability and method of test sequence generation

Abstract

The invention provides a method of design for testability at RTL which can guarantee high fault coverage and a method of test sequence generation for easily generating test sequences for an RTL circuit which is designed to be easily testable by the method of design for testability. In the RTL circuit, scannable registers are selected so that the RTL circuit can attain an easily testable circuit structure such as an acyclic structure. This RTL circuit is timeframe expanded on the basis of a predetermined evaluation function and logically synthesized, so as to generate a timeframe expanded combinational circuit, that is, a gate level timeframe expanded circuit, as a circuit for test sequence generation. For the timeframe expanded combinational circuit, test patterns for multiple stuck-at faults are generated, the test patterns are transformed into test sequences on the basis of data on timeframes including primary inputs and pseudo-primary inputs, and the test sequences are transformed into scanning test sequences in view of a scan shift operation.