Binary and decimal adder unit

Abstract

A binary and decimal adder unit uses a pre-sum logic for generating pre-sums of the operands A, B under the presumption of one and zero carry inputs into the decimal digit position, and also uses a digits carry network for generating binary carries within the decimal digit positions and a high order carry out signal of said plurality of decimal digits. Each decimal digit position of said adder unit provides a six correction and a pre-sum selection. The pre-sum logic comprises a carry prediction logic for generating decimal digit position carry out signals on the presumption of a zero carry input and of a one carry input into the decimal digit. In response to gating signals derived from the carry out signals of the carry prediction logic and operation control signals a pre-selection is performed for selecting a qualified pre-sum generated on the presumption of a zero carry input into the decimal digit, and for selecting a qualified pre-sum generated on the presumption of a one carry input into the decimal digit. The pre-selection of the qualified pre-sums is performed for all decimal digit positions in parallel to the generation and distribution of the carries in the digits carry network over the total of decimal digit positions. The pre-sum selection logic further comprises a two way selector which is responsive to a digit carry-in signal from the digits carry network for selecting one the qualified pre-sums as the correct sum of the digit position. According to one embodiment of the invention, the pre-sum logic generates six corrected pre-sums which are included in the pre-selection of qualified pre-sums.