The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 18, 2001
Filed:
Jun. 30, 2000
Koji Kato, Yokohama, JP;
Masahiro Kamoshida, Yokohama, JP;
Shigeo Ohshima, Yokohama, JP;
Hiroyuki Ohtake, Tokyo, JP;
Kabushiki Kaisha Toshiba, Kawasaki, JP;
Abstract
A clock synchronous circuit comprising a clock receiver, a delay monitor, a forward pulse delay circuit, a backward pulse delay circuit, a driver, a state-holding section, a control signal generating circuit, a first AND circuit, and a second AND circuit. The delay monitor delays the output of the clock receiver. The forward pulse delay circuit delays the output of the delay monitor. The backward pulse delay circuit delays the output of the clock receiver. The driver receives the output of the backward pulse delay circuit and outputs an internal clock signal. The state-holding section controls the backward pulse delay circuit. The control pulse generating circuit initializes the forward pulse delay circuit. The first AND circuit is provided for controlling the supply of the output of the clock receiver to the delay monitor. The second AND is provided for controlling the supply of the output of the delay monitor to the forward pulse delay circuit.