Low power glitch-free clock switch

Abstract

A glitch-free clock switch circuit for an integrated circuit having a plurality of asynchronous clocks, wherein only one clock is selected at a time, and wherein the clock switching circuitry for switching from a currently selected clock to an inactive clock to next be selected is activated only for the time it takes to complete the switching. The clock switch circuit includes at least three sets of clock drivers, wherein each set is comprised of two drivers and separate clock drivers are each associated with the output clock, the currently selected clock and the clock to next be selected, respectively. An edge detector turns on these clock drivers in response to a clock select signal, and a set of synchronizers receive and synchronize the clock select signal first with the output clock and then with the currently selected clock and the clock to next be selected, respectively. A plurality of logic gates switches the clock output from the selected clock to the clock to next be selected by the clock select signal. A reset circuit turns off the clock drivers once the clock output has been switched from the selected clock to the clock to next be selected. The clock drivers for clocks that are not selected are turned off during and after the period of time the selected clock is switched to the clock to next be selected. Once the switching is complete, the entire clock switching circuit is turned off until another clock switching occurs.