Differential current mirror with low or eliminated differential current offset

Abstract

The invention relates to a differential current mirror circuit with low or eliminated differential current offset. The circuit comprises first and second input transistors Q,and Q,i whose physical layout is being matched and emitters connected together to a first reference voltage V,through an input resistance means R,; first and second output transistors Q,and Q,whose physical layout is being matched and emitters connected together to a second reference voltage V,through an output resistance means R,; collector and base of the first (second) input transistor Q,(Q,) being connected to the base of the first (second) output transistor Q,(Q,) and to a first (second) input current terminal to which a first (second) input current i,(i,) is being supplied; and collector of the first (second) output transistor Q,(Q,) being connected to a first (second) output current terminal generating first (second) output current i,(i,). By using only one input and one output regeneration resistors and providing that the layout of the input and output transistors is matched in pairs, the output differential current offset of the circuitry is eliminated. A cascade of differential current mirror connected in series is also provided.