The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 18, 2001
Filed:
May. 12, 1999
Asim Selcuk, Cupertino, CA (US);
Advanced Micro Devices, Inc., Sunnyvale, CA (US);
Abstract
A device and method for reducing parasitic capacitance between the gate and an adjacent conductive layer. A gate structure is provided having a polysilicon layer with recessed side portions. Sidewalls or spacers partially cover the sides of the polysilicon layer, while the exposed side portions of the polysilicon layer are etched to form the recessed side portions. The area that is etched away to form the recessed side portions accounts for the reduction in intra-level parasitic capacitance between the gate and adjacent conductive layers, such as local interconnect layers, interconnect layers, and contact layers. By removing the area etched away to form the recessed side portions, the separation between the gate and the conductive layer is increased, thereby inhibiting parasitic capacitance which, among other factors, is a function of the distance between two electrical components. Consequently, the present invention provides a simple device and method of reducing the parasitic capacitance of the semiconductor device without sacrificing valuable semiconductor space.