The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 18, 2001
Filed:
Jun. 11, 1999
Chi-Jung Huang, Saratoga, CA (US);
Helen Peng, Sunnyvale, CA (US);
Ken Ming Li, Santa Clara, CA (US);
S3 Graphics Co., Ltd., Cayman Islands, BWI, KY;
Abstract
On-chip resistance, capacitance and/or inductance is implemented in an integrated circuit in vertical configurations using stacked vias and medullization layers within the integrated circuit. Column shaped openings or vias are formed within the integrated circuit and connect from a silicon substrate to various metal traces. The vias are filled with conductive material such as platinum or tungsten. Parallel vias are used to form capacitance, while multiple vias and metal traces are arranged in various patterns over several planes in order to form resistance and/or inductance. The use of the stacked vias and metal traces in a vertical fashion reduces lateral spacing required to implement on-chip resistance, capacitance and/or inductance and allows for more efficient use of space in very large scale integration.