The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 11, 2001

Filed:

Feb. 20, 1998
Applicant:
Inventor:

Guy Dupenloup, Marly-le-Roi, FR;

Assignee:

LSI Logic Corporation, Milpitas, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/750 ;
U.S. Cl.
CPC ...
G06F 1/750 ;
Abstract

A method of determining circuit characteristics of an integrated circuit design as defined by a generic netlist comprising the steps of identifying hardware elements in the generic netlist, determining key characteristics for each of said identified hardware elements, determining interconnections of said identified hardware elements, and detecting the degree of conformity of said identified hardware elements, said key characteristics, and said interconnections to predetermined configurations. The systems further identifies all cells in the generic netlist, determines for each cell the type of cell, accumulates cell types and cell type counts, and notifies an operator of said accumulated values.


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