Fast-scan-flop and integrated circuit device incorporating the same

Abstract

Disclosed is a scan-flop adapted for use in testing integrating of an integrated circuit's core logic and an integrated circuit device incorporating the same. Broadly, the scan-flop comprises a synchronous flip-flop having at least one input adapted to receive selected input data from input terminals of the scan-flop and at least one output operative in response to presence of a clocked enable signal to exhibit a logic state as determined by the selected input data. This output defines a data output terminal for the scan-flop. A logic circuit (e.g., an inverter) is electrically coupled to the flip-flop output and has an output node defining a scan output terminal for the scan-flop, which enables a substantial reduction in capacitive loading due to a scan test. A multiplexer operates in response to a select signal to transmit the selected input data to the flip-flop's input. An integrated circuit device is also disclosed having a plurality of I/O pins defined on a semiconductor die and a logic core disposed therein. The logic core includes at least a first logic chain electrically connected between I/O pins and broadly includes two scan-flops and a logical array electrically interposed therebetween.