The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 11, 2001
Filed:
Nov. 06, 1998
Applicant:
Inventor:
Gary M. Godfrey, Austin, TX (US);
Assignee:
Advanced Micro Devices, Inc., Sunnyvale, CA (US);
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/12 ;
U.S. Cl.
CPC ...
G06F 1/12 ;
Abstract
An on-chip programmable delay line is provided for controlling timing of an embedded system. A delay register is coupled to a processor. The delay register stores a delay or control value responsive to the processor. The on-chip programmable delay line is coupled to the delay register and delays a signal responsive to the delay value. The relationship between dynamic random access memory (DRAM) signals, such as row address strobe (RAS) and column address strobe (CAS), can thus be adjusted. In addition, the on-chip programmable delay line can be utilized with a device that includes an input that is not synchronous to a system clock.