The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 11, 2001
Filed:
Nov. 06, 1998
Peter Chambers, Phoenix, AZ (US);
Swaroop Adusumilli, Tempe, AZ (US);
Subramanian S. Meiyappan, Tempe, AZ (US);
VLSI Technology, Inc., San Jose, CA (US);
Abstract
A system and method for completing a read transaction between an initiator device and a host memory device in a computer system, in which the present invention optimizes the retry behavior of the initiator device and a target device. The system of the present invention includes a bus bridge device, wherein the bus bridge device includes a target device coupled to the initiator device via a bus; the host memory device coupled to the bus bridge device; and a timer mechanism coupled to the target device. The initiator device is adapted to initiate a present read transaction via the target device, such that an access is asserted between the initiator device and the target device. The timer mechanism is adapted to measure target latency for one or more read transactions preceding the present read transaction, and the timer mechanism is further adapted to use the target latency to calculate a dynamic target latency period. The target device is adapted to maintain the access to the initiator device during the dynamic target latency period. Thus, in accordance with the present invention, the target latency is dynamically measured and used to optimize the retry behavior of the initiator and target devices.