The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 11, 2001
Filed:
Aug. 04, 2000
Paul H. OuYang, San Jose, CA (US);
Donald Liusie, San Jose, CA (US);
DMEL Incorporated, Santa Clara, CA (US);
Abstract
The precharge operation of a DRAM array in a non-multiplexed address interface is controlled so that the DRAM is precharged only if there is a change in the word line address. By precharging the DRAM only when a new word line is asserted, a significant power savings may be obtained. An activity monitor compares each new word line address with the previous word line address. If the activity monitor indicates that a new word line is asserted, a timing control circuit will precharge the DRAM, including equalizing the bit lines. If the activity monitor indicates that the word line is not changed, the timing control circuit does not precharge the DRAM. The timing control circuit includes a dummy precharge circuit and initiates a dummy precharge cycle in the beginning of each new cycle for timing purposes. The timing control circuit initiates the active cycle after the dummy precharge cycle regardless of whether a new word line is asserted or not.