Programmable delay circuit

Abstract

A programmable delay circuit employs a relatively slow conventional silicon emitter-coupled transistor pair and a relatively fast silicon/germanium heterojunction emitter-coupled transistor pair. The bases of both transistor pairs are driven by an input signal to be delayed. The collectors of transistors of both pairs are linked to a voltage source through a pair of load resistors, with an output signal appearing across the collectors of both transistor pairs. A current source draws complementary adjustable load currents through the two transistor pairs. Although the sum of the two load currents is a constant, the relative amount of load current drawn though the two transistor pairs is adjustable. The silicon transistors have a substantially lower peak F,than the silicon/germanium transistors, and the sum of the load currents the current source draws through the collector-emitter paths of the transistor pairs is selected so that when the silicon/germanium transistor pair conducts all of the load current they operate near their peak F,and switch near their maximum speed. However when the silicon transistor pair conducts all of the load current, the silicon transistors operate substantially below their peak F,and therefore switch at much less than their maximum speed. The delay between state changes in the input and output signals is determined by the relative amount of load current supplied to each transistor pair.