The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 11, 2001
Filed:
Apr. 07, 1999
National Science Council of Republic of China, Taipei, TW;
Abstract
A CMOS pulse shrinking delay element with deep subnanosecond resolution applicable to a Time-to-Digital Converter (TDC) can control its pulse shrinking or expanding capability be adjusting the dimension ratio between internal adjacent elements. This eliminates the need in prior CMOS pulse shrinking delay elements to adjust an external bias voltage or continuously calibrate the element in order to control pulse shrinking or expanding capabilities, facilitates simplification of circuits using the delay element, permits more precise design and control of the pulse shrinking or expanding capabilities of every element in a TDC circuit, and in practice reduces single shot errors in a cyclic TDC utilizing the pulse shrinking delay element to on the order of ten picoseconds, resulting in a TDC having extremely fine resolution, excellent accuracy, low power consumption, and low sensitivity to supply voltage and ambient temperature variations.