Semiconductor device using external power voltage for timing sensitive signals

Abstract

A semiconductor device receiving a stable external power voltage includes a reduced-voltage-generation circuit which generates an internally reduced power voltage, an input circuit which operates based on the internally reduced power voltage, causing the internally reduced power voltage to fluctuate, a clock-control circuit which generates an internal clock signal, an output circuit which outputs a data signal to an exterior of the device at output timings responsive to the internal clock signal, a clock-delivery circuit which conveys the internal clock signal from the clock-control circuit to the output circuit, and operates based on the external power voltage such as to make the output timings substantially unaffected by fluctuation of the internally reduced power voltage.