The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 11, 2001
Filed:
Jun. 29, 2000
Herman Joris Casier, Kuurne, BE;
Alcatel, Paris, FR;
Abstract
An interface arrangement including the cascade connection of a differential pre-amplifier (HPA,, HPA,) and a comparator (DA), and generally known as fast Low Voltage Differential Signal [LVDS] circuit for interfacing electronic chips. The current standards for such a LVDS circuit specify a minimum switching threshold voltage for the small differential input signal, while the common mode input signal varies over a very large range, both at a very high frequency. This is achieved owing to the fact that the differential pre-amplifier comprises a first (HPA,) and a second (HPA,) half pre-amplifier, each receiving the arrangement inputs (INN, INP) in an opposite way. Each half pre-amplifier (HPA,/HPA,) having first input inverter means (NN,, PN,) coupling an input (INN/INP) to an output (OUT,/OUT,) thereof, and second input inverter means (NP,, PM,, PM,; PP,, NM,, NM,) coupling the other input (INP/INN) to the output via current mirror means (PM,, PM,; NM,, NM,). The output current of the second input inverter means is thereby inverted with respect to the output current of the first input inverter means. To obtain a controlled gain, the half pre-amplifier further includes a short-circuited inverter.