The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 11, 2001
Filed:
Jun. 29, 1999
Ulrich Sieben, Reute, DE;
Günter Igel, Teningen, DE;
Mirko Lehmann, Freiburg, DE;
Hans-Jürgen Gahle, Emmendingen, DE;
Bernhard Wolf, Stegen, DE;
Werner Baumann, Freiburg i.Br., DE;
Ralf Ehret, Merdingen, DE;
Micronas GmbH, Freiburg, DE;
Abstract
A chip arrangement (,) has a substrate board (,) with an opening (,), into which a carrier chip (,) is inserted, which has an electrical or electronic structural component (,). At least one conductor path (,) is integrated into the carrier chip (,), which connects the structural component (,) to the electrical connection contact (,). The carrier chip (,) is inserted into the opening (,) in such a way that its ends project beyond the opposite-facing, flat-sided surfaces (,′) of the substrate board (,), and thereby form overhangs (,′). Here, the structural component is arranged on the overhang (,) projecting beyond the one surface (,), and the connection contact (,) is arranged on the overhang (,′) projecting beyond the other surface (,′), and the conductor path (,) connecting the structural component (,) and the connection contact (,) passes through the opening (,). A seal is arranged between the substrate board (,) and the carrier chip (,).