The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 04, 2001
Filed:
Oct. 22, 1998
Applicant:
Inventors:
Tokuya {overscore (O)}sawa, Tokyo, JP;
Hideshi Maeno, Tokyo, JP;
Assignee:
Mitsubishi Denki Kabushiki Kaisha, Tokyo, JP;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01R 3/128 ;
U.S. Cl.
CPC ...
G01R 3/128 ;
Abstract
When the RAM (,) is not initialized, data signals captured from the data output portions (do[n]) may include undefined value, but these data signals are not transferred to an MISR through the scan path (,). Transferred to the MISR are only the data signals (DI[n]) captured by the scan path (,). Accordingly, BIST can be applied to the combinational logic circuit (,) without requiring initialization of the RAM (,) and without being affected by undefined value. Thus, BIST to the combinational logic circuit (,) can be normally achieved in a short period.