10/100 mb clock recovery architecture for switches, repeaters and multi-physical layer ports

Abstract

A clock recovery architecture for recovering clock and serial data from an incoming data stream of a local area network station. A phase picker architecture augmented by a phase interpolator is used as part of the clock recovery architecture to enhance phase resolution. A single clock generation module (CGM) and N phase multiplexers, one for each clock recovery channel on a chip, is used to select one of M phases of a 250 Mhz clock signal from the CGM for each clock recovery channel. To provide the required phase resolution, a phase interpolator is used. The phase interpolator is used to create a number of delay steps evenly spaced between the gross phase steps of the phase multiplexer. Each phase multiplexer is advanced or retarded in response to the pump-up (pumpup) or pump-down (pumpdn) signals from each clock recovery channel (CRM).