The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 04, 2001

Filed:

Mar. 27, 1998
Applicant:
Inventor:

Masanori Kajitani, Gifu, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 1/606 ;
U.S. Cl.
CPC ...
G11C 1/606 ;
Abstract

Disclosed is a non-volatile semiconductor memory apparatus, having floating gate electrodes, from which multi-value data can be accurately read out. A memory cell transistor (,) is provided in a row with a plurality of reference transistors (,), and a plurality of such rows are selectively connected by a word line (,). Reference potentials (Va˜Vc) are written to the reference transistors (,) simultaneous to the writing of data to the memory cell transistor (,). In read mode, following the completion of the writing operation, memory data is determined by comparing reference potentials (VR,˜VR,) which have been read out from the reference transistors (,), with a potential (VBL) which has been read out from the memory cell transistor (,).


Find Patent Forward Citations

Kajitani, Masanori. (2001). Non-volatile semiconductor memory apparatus (U.S. Patent No. 6285589). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6285589

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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