The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 04, 2001

Filed:

Sep. 20, 1999
Applicant:
Inventor:

Kevin Lyne, Plano, TX (US);

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H05K 7/02 ;
U.S. Cl.
CPC ...
H05K 7/02 ;
Abstract

A routing technique for improving device reliability by selectively depopulating solder balls (,) (and their respective solder ball pads (,), vias (,) and traces or lines (,)) from a conventional foot print of a ball grid array (BGA) package, and a BGA package so modified. The routing technique uses the gap resulting from the depopulated solder balls as additional space for routing traces or lines from solder ball pads to an exterior surface of a substrate (,) upon which a semiconductor die (,) is mounted. An advantage of the present invention is that it permits the retention of an optimum via diameter while increasing the number of solder balls on ever shrinking packages, thereby increasing device reliability.


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