The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 04, 2001

Filed:

Mar. 12, 1999
Applicant:
Inventors:

Kosaku Ichikawa, Tokyo, JP;

Tateo Koyama, Saitama-ken, JP;

Hitoshi Matsumura, Kanagawa-ken, JP;

Shinji Sato, Tokyo, JP;

Assignee:

Kabushiki Kaisha Toshiba, Kawasaki, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K 1/704 ;
U.S. Cl.
CPC ...
H03K 1/704 ;
Abstract

A gate control circuit for turning on and off an insulated gate semiconductor device having gate, emitter and collector terminals, including a first DC power source coupled to the gate terminal via a first switch and configured to apply a positive voltage to the gate terminal in order to turn on the insulated gate semiconductor device when the first switch is turned on and the second switch is turned off; a second DC power source coupled to the gate terminal via a second switch and configured to apply a negative voltage to the gate terminal in order to turn off the insulated gate semiconductor device when the second switch is turned on and the first switch is turned off; a parallel circuit of a diode and a capacitor coupled in series to the second switch; and a turn off assist circuit configured to produce a negative charge on the capacitor to assist in turning off the insulated gate semiconductor device. In a power converter circuit having a plurality of insulated gate semiconductor devices, equalization of delay times for turning off the insulated gate semiconductor devices is achieved by controlling a charged stored in the capacitor of each gate control circuit based on detected collector-emitter voltages or detected emitter currents.


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