Delay locked loop circuits and methods of operation thereof

Abstract

A delay locked loop circuit includes a variable delay circuit that receives an input clock signal and produces a delayed clock signal that is variably delayed with respect to the input clock signal responsive to a delay control signal applied to the variable delay circuit. A delay control circuit is responsive to the input clock signal and to the delayed clock signal, and applies a delay control signal to the variable delay circuit based on a comparison of an edge of the delayed clock signal corresponding to a first edge of the input clock signal to a second edge of the input clock signal that follows the first edge of the input clock signal. In an embodiment, the delay control circuit includes a phase comparator circuit that receives the input clock signal and the delayed clock signal and produces a phase comparison signal that indicates whether the edge of the delayed clock signal corresponding to the first edge of the reference clock signal leads or lags the second edge of the input clock signal. A delay control signal generating circuit applies a delay control signal to the variable delay circuit responsive to the phase comparison signal. Related operating methods also are provided.