The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 04, 2001
Filed:
Aug. 04, 2000
Christophe Gaillard, Saint Pancrasse, FR;
Stéphane Le Tual, Veurey Voroize, FR;
Atmel Grenoble S.A., Saint Egreve, FR;
Abstract
A sample-and-hold device comprises a sampling transistor (Q,) and a sampling capacitor (C,), the sampling transistor being off in hold mode in order to prevent the discharging of the sampling capacitor and conductive in sampling mode to apply a voltage to the capacitor that is substantially equal to the voltage (V,) at its base. In order to apply a cut-off voltage to this base, in off mode, that is equal to the voltage present at the sampling capacitor, there is provided a circuit comprising, in series, between two power supply terminals, two MOS type transistors (MP,, MP,) having drain-source channels substantially with the same width-to-length ratio, a bipolar transistor (Qcl) having its base connected to the junction point of the two MOS transistors and its emitter connected to the base of the sampling transistor (Q,), and a diode (D,) biased by a current (Ip), connected between the source and the gate of one of the two MOS transistors (MP,), the gate of the other transistor (MP,) being connected to the sampling capacitor. This device can be applied especially to samplers used upline to an analog-digital converter.