The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 04, 2001

Filed:

May. 10, 2000
Applicant:
Inventors:

Sang Hoo Dhong, Austin, TX (US);

Hung Cai Ngo, Austin, TX (US);

Jaehong Park, Kyunggi-Do, KR;

Osamu Takahashi, Round Rock, TX (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K 1/9094 ;
U.S. Cl.
CPC ...
H03K 1/9094 ;
Abstract

A method and apparatus for implementing dynamic logic with programmable dynamic logic gates acts as a complement to programmable logic arrays (PLAs) used in high-speed microprocessor designs. A matrix of selectable cells provides powerful logic functions such as AND-OR gate capability with a minimum of inputs and transistors. By using programmable logic arrays and programmable dynamic gates, the efficiency of a logic block can be dramatically improved with little added circuit area.


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Dhong, Sang. (2001). Method and apparatus for implementing logic using mask-programmable dynamic logic gates (U.S. Patent No. 6285218). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6285218

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