Digital phase-locked loop circuit with reduced phase jitter frequency

Abstract

A digital phase-locked loop (DPLL) (,) for use in one or more integrated circuits (,) that may be combined within an electronic system is disclosed. The DPLL (,) includes a phase detector (,) that generates a shift clock and a shift direction signal responsive to a phase difference between a system clock and a feedback clock. The shift direction signal is stored in a latch (,), applied to one input of an exclusive-NOR gate (,), and to shift direction inputs (R/{overscore (L)}) of first and second digital delay lines (,). The first digital delay line (,) receives the system clock and generates a delayed clock that is distributed within the integrated circuit (,) by clock distribution circuitry, and that is applied to an input of the second digital delay line (,); the second digital delay line (,) generates the feedback clock that is received by the phase detector (,). The shift clock is gated from application to the first and second digital delay lines according to the comparison of the current shift direction with that stored in the latch (,), such that the shift clock is applied to the shift clock input of the first digital delay line (,) to adjust its delay only upon the phase detector (,) detecting a phase differential of the same polarity at least twice in a row; the shift clock is applied to the shift clock input of the second digital delay line (,) upon the phase detector (,) detecting opposite phase differentials in the current and previous phase detection events.