The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 28, 2001

Filed:

Aug. 23, 1999
Applicant:
Inventors:

Seung Hee Lee, Kyoungki-do, KR;

Seok Lyul Lee, Seoul, KR;

In Cheol Park, Seoul, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G02F 1/136 ;
U.S. Cl.
CPC ...
G02F 1/136 ;
Abstract

The present invention provides a liquid crystal display having high aperture ratio and high transmittance, which prevents signal delay in the gate bus line and also improves the intensity of fringe field, and the method of manufacturing the same. The liquid crystal display is manufactured according to the steps of: forming a gate bus line and a common signal line on a lower substrate; forming a gate insulating layer on the lower substrate in which the gate bus line and the common signal line are formed; forming a channel layer on a selected portion of the gate insulating layer comprising the gate bus line; forming a source and a drain electrodes so as to overlap with both sides of the channel layer, and a data bus line being arranged perpendicular to the gate bus line; etching the gate insulating layer so as to expose a selected portion of the common signal line; forming a counter electrode by depositing an ITO layer on the gate insulating layer, and by patterning a selected portion thereof so as to contact with the exposed common signal line; depositing a passivation layer over the gate insulating layer in which the counter electrode is formed; etching the passivation layer so as to expose a selected portion of the drain electrode; and forming a pixel electrode, by depositing the ITO layer on the passivation layer so as to contact to the exposed drain electrode, and by patterning a selected portion of the ITO layer so that a fringe field is formed by being overlapped with the counter electrode.


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