The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 28, 2001

Filed:

Mar. 04, 1998
Applicant:
Inventors:

James R. Webb, Boulder, CO (US);

Ron C. Simpson, Erie, CO (US);

Assignee:

Display Laboratories, Inc., Boulder, CO (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04N 9/28 ;
U.S. Cl.
CPC ...
H04N 9/28 ;
Abstract

Disclosed is a high-speed approximation device that generates zone correction values in both the horizontal and vertical directions. Group correction values are stored for specific physical locations on the screen for each correction factor parameter. Higher resolution correction signals can be produced by generating zone correction values. Zone correction values are produced for binary fractional addresses that correspond to specific physical locations on the screen. By addressing specific binary fractional addresses that correspond to the location of the video image on the screen, new group correction values do not have to be produced each time the horizontal or vertical size or centering or frequency of the video image is changed. Additionally, by using start addresses and end addresses, zone correction values only have to be produced for the area which the video image occupies on the screen. The present invention also uses a high-speed binary fractional multiplier that multiplies a correction value by a series of binary numbers that simply shift the decimal location of the correction value to produce quotient values. Selection of the quotient values is made by a binary fractional address signal that indicates the specific address for the zone correction value to be generated. By transforming from an arbitrary line count address space to a binary physical address space, the present invention allows for the use of a simple and fast parallel binary fractional multiplier engine.


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