The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 28, 2001

Filed:

Jun. 02, 1995
Applicant:
Inventors:

Victor M. DaCosta, San Jose, CA (US);

Alan G. Lewis, Sunnyvale, CA (US);

Assignee:

Xerox Corporation, Stamford, CT (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G09G 5/00 ;
U.S. Cl.
CPC ...
G09G 5/00 ;
Abstract

A product such as a display includes a first substrate on which array circuitry and multiplexer circuitry are formed and also includes one or more integrated circuit (IC) structures attached to the first substrate. The array circuitry includes N data lines, each driven by multiplexed signals, where N is greater than 32. The multiplexer circuitry provides the multiplexed signals in response to analog drive signals from P analog input leads and multiplexer control signals from Q control leads, where P is less than N but not less than 32 and where Q is less than N but not less than N/P. Each of R IC structures can includes a single crystal substrate, each with digital-to-analog converting (DAC) circuitry, where R is greater than zero. Each substrate has at least S analog output leads, where S is not less than 32. Together, the R IC structures have T analog output leads, where T is greater than P, and each of the P analog input leads is paired with and connected to one of the T analog output leads. The array circuitry and multiplexer circuitry can include polysilicon thin-film transistors (TFTs) on a glass substrate. The IC structure can be attached to the glass substrate using tape-automated bonding (TAB) or chip-on-glass (COG) techniques. This architecture makes it possible to use commercially available DAC ICs and significantly reduces the number of external chips required to drive the array as the number of pixels in the array increases.


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