Direct digital synthesis using a sine weighted dac

Abstract

The present invention provides a novel direct digital synthesis system architecture which employs a numerically-controlled oscillator (NCO), some decoding logic, and a sine-weighted digital-to-analog converter (DAC) with significantly fewer output values required than conventional DDS systems to provide improved spurious performance (relative to the number of bits of resolution required of the DAC), extended frequency of operation, reduced chip area, and reduced power consumption relative to conventional DDS techniques. The output of the decoder is input to a sine-weighted digital-to-analog converter (DAC). Importantly, the sine-weighted DAC outputs a constant number of samples per cycle using a relatively few number of taps. Although there are significantly fewer taps in the sine-weighted DAC as compared to the linear DAC in conventional DDS systems, each tap of the sine-weighted DAC has a high degree of accuracy, e.g., 16-18 bits. Accordingly, a constant number of sample values are repetitively used in the stepped approximation of a sine wave, regardless of output frequency, significantly reducing the number of discrete output values that a digital-to-analog converter (DAC) is otherwise required to produce. Unlike conventional direct digital synthesis (DDS) architectures which use linear digital-to-analog converters having many bits of resolution, the present invention provides a sine-weighted digital-to-analog converter having relatively few taps to produce a constant number of samples per cycle, eliminating the conventional need for a memory-based sine wave look-up table.