The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 28, 2001

Filed:

Sep. 08, 1997
Applicant:
Inventors:

Hiroki Miura, Warabi, JP;

Yasuhito Koumura, Tokyo, JP;

Kenshi Matsumoto, Koshigaya, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/04 ;
U.S. Cl.
CPC ...
G06F 1/04 ;
Abstract

A clock control method is proposed, in which malfunctions caused by clock skews are decreased when the same high-speed clock is used inside and outside an IC. An original clock is input via CKIN, with the return path of an output buffer connected to an input buffer in an input/output buffer. The clock, once output via the output buffer, returns to the IC as a reentry clock. The selected reentry clock or original clock are used in the IC. The clock appearing at SYSCK is used in an external circuit. By using the reentry clock in the IC, the clock skew corresponding to the delay of the output buffer can be decreased.


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Miura, Hiroki. (2001). Clock control method and integrated circuit element manufactured by using same (U.S. Patent No. 6281733). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6281733

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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