Fine-tuning phase-locked loop pll using variable resistor between dual pll loops

Abstract

A clock generator uses two PLL loops and a variable resistor to generate a variable output frequency from a single fixed-frequency reference clock. Each PLL loop receives the reference clock and phase-compares it with a feedback clock. The feedback clock in one loop is slightly faster in frequency than the feedback clock in the second loop. The input voltages to voltage-controlled oscillators (VCOs) in the two loops thus vary slightly. A variable resistor is connected between the two inputs to the VCOs. The variable resistor has a center tap that can be selected from locations along the variable resistor. The center tap voltage is input to a final VCO that generates the variable output frequency. The output frequency is varied by selecting the center tap's location along the variable resistor. The variable resistor can be constructed from a series of sub-resistors with the center-tap location chosen by select transistors acting as a multiplexer.