Programmable frequency divider

Abstract

We have recognized that the design and programming complexity associated with conventional frequency divider configurations can be significantly reduced by a configuration of functionally identical, modular division blocks which are each able to swallow at least one input cycle of a input signal by switching to a phase-lagging output once per output cycle. The number of input pulses swallowed when a division block switches to a lagging waveform is a direct function of the division block's location in the chain, such that the number of input cycles swallowed per phase switch increases moving down the chain of division blocks. Therefore, the chain of division blocks has discrete elements for achieving most-significant to least-significant division factor increments. The total number of input cycles swallowed by the chain of division blocks equals the sum of cycles swallowed by each division block. Thus, to achieve a variety of division factors, a controller controls which, if any, division blocks switch to a phase-lagging waveform once each output cycle. Furthermore, we have recognized that the range of division factors which may be achieved by the chain of frequency dividers can be increased by controlling at least one division block to switch to a phase-leading waveform once each output cycle.