The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 28, 2001

Filed:

Dec. 08, 1999
Applicant:
Inventors:

David M. Thomas, Los Altos, CA (US);

Richard J. Reay, Mountain View, CA (US);

Assignee:

Linear Technology Corporation, Milpitas, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 2/702 ; H03K 5/00 ; H03K 1/700 ;
U.S. Cl.
CPC ...
G11C 2/702 ; H03K 5/00 ; H03K 1/700 ;
Abstract

Circuits and methods are provided that compensate for dynamic errors caused by voltage drops across a switch coupled in series with a capacitor in an electrical circuit such as a track-and-hold circuit. In such circuits, the capacitor should provide the same voltage as a signal coupled to the switch, but does not because of the switch voltage drop. The switch can be, for example, a MOSFET or more particularly a CMOS device. Dynamic errors are compensated for by measuring the voltage drop across the switch and then effectively adding the measured voltage drop to a voltage provided by the capacitor.


Find Patent Forward Citations

Thomas, David. (2001). Dynamic error compensation in track-and-hold circuits (U.S. Patent No. 6281717). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6281717

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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