The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 28, 2001
Filed:
Oct. 15, 1999
Timothy P. Layman, Danville, CA (US);
Silicon Graphics, Inc., Mountain View, CA (US);
Abstract
A system and method for providing power to the gates of a semiconductor chip routes power and ground from one layer of the chip to another layer of the chip using a first metal strip located at a first metal layer and a second metal strip located at a second metal layer, wherein the second metal layer is not directly adjacent to the first metal layer. A stacked via is used to connect the first metal strip to the second metal strip. The stacked via may comprise, for example, a first via connecting the first metal strip to an intermediate metal strip and a second via connecting the intermediate metal strip to the second metal strip. Alternatively, the stacked via may comprise a plurality of vias connecting the first metal strip to the intermediate metal strip and a plurality of vias connecting the intermediate metal strip to the second metal strip. The system and method avoids using long, parallel metal strips on each layer of the chip to route power and ground from one layer of the chip to another layer of the chip.